/*
 * $Header: /smsa/bsd:include/dev/zscc.h:bsd  1.6  $
 * $Source: /smsa/bsd:include/dev/zscc.h: $
 *
 * Copyright (c) 1988 Acorn Computers Ltd., Cambridge, England
 */

#ifndef __dev_zscc_h
#define __dev_zscc_h

/*
 *	Z 8530 SCC description.
 */

#define ZSCC_CON_SPEED	0xF			/* 4 bit field */
#define ZSCC_SPEED_EXT	0x0			/* 16x external clock */

#define ZSCC_SPEED_50	0x1
#define ZSCC_SPEED_75	0x2
#define ZSCC_SPEED_110	0x3
#define ZSCC_SPEED_134	0x4
#define ZSCC_SPEED_150	0x5
#define ZSCC_SPEED_300	0x6
#define ZSCC_SPEED_600	0x7
#define ZSCC_SPEED_1200	0x8
#define ZSCC_SPEED_1800	0x9
#define ZSCC_SPEED_2400	0xA
#define ZSCC_SPEED_3600	0xB
#define ZSCC_SPEED_4800	0xC
#define ZSCC_SPEED_7200	0xD
#define ZSCC_SPEED_9600	0xE
#define ZSCC_SPEED_19200 0xF

/*
 *	Where the thing lives in A680 I/O space
 */

#define	ZSCC_CONT	((volatile unsigned char *)(0x032B0008))
#define	ZSCC_DATA	((volatile unsigned char *)(0x032B000C))

#define	ZR0_RXCA	0x01		/*  Character avail  */
#define	ZR0_TXBE	0x04		/*  Xmit buffer empty */
#define	ZR0_DCD		0x08		/*  DCD interrupt */
#define	ZR5_SENDB	0x10		/*  Send break */
#define	ZR5_DTR		0x80		/*  DTR  */
#define	ZR5_BITS	0x60		/*  Character Size (TX)   */
#define	ZR3_BITS	0xC0		/*  Bits  */
#define	ZR5_5BITS	0x00		/*  The values here look funny */
#define	ZR5_6BITS	0x40		/*  but reflect the hardware's */
#define	ZR5_7BITS	0x20		/*  peculiarities exactly! */
#define	ZR5_8BITS	0x60
#define	ZR3_5BITS	0x00
#define	ZR3_6BITS	0x80
#define	ZR3_7BITS	0x40
#define	ZR3_8BITS	0xC0
#define	ZR4_PARENB	0x01
#define	ZR4_EVENP	0x02

#define	ZR1_FRAMERR	0x40
#define	ZR1_OVERRUN	0x20
#define	ZR1_PARITY	0x10

#endif/*__dev_zscc_h*/

/* EOF zscc.h */
