/* ps_irq.h
 *
 * SCSI Interrupt Handler Definitions
 *
 * $Header: /smsa/bsd:include/dev/ps_irq.h:bsd  1.13  $
 * $Source: /smsa/bsd:include/dev/ps_irq.h: $
 *
 * Copyright (c) 1989 Acorn Computers Ltd., Cambridge, England
 *
 */

#ifndef	__dev_ps_irq_h
#define	__dev_ps_irq_h


#if 0
/* all unwanted messages in here */
#define SOFT_MESSAGES
#define DRIVER_MESSAGES
#define MESSAGES
#define IRQ_MESSAGES
#define DISPLAYING
#define DMAC_MESSAGES
#define COPY_MESSAGES
#endif

#if 1
/* all wanted messages in here */
#endif

/* Description of the Hardware */

#define    MODULE_BASE    (0x03000000)
#define    PODULE_BASE    (0x03340000)
#define    ADDRESS_SPACE  (0x00004000)

/* I/O Devices mapped in Module Space */
#define    SBIC           (0x00002000)
#define    DMAC           (0x00003000)

/* I/O Devices mapped in Podule Space */
#define    PAGE_REG       (0x00003000)
#define    INT_STAT       (0x00002000)
#define    CLR_INT        (0x00002000)

/* Bits defined in the Page Register */
#define    PR_RESET             (0x80)
#define    PR_ENABLE_IRQ        (0x40)
#define    PR_SHUTDOWN		(0x00)

/* Bits in the interrupt latch */
#define SBIC_IRQ                (0x08)
#define DMAC_IRQ                (0x02)

/* Sense of interrupts [currently active HI] */
#define SBIC_INT             SBIC_IRQ
#define DMAC_INT             DMAC_IRQ

/* A Definition of the SBIC */

#define    SC_OWN_ID            0x00
#define    SC_CONTROL           0x01
#define    SC_TIMEOUT           0x02
#define    SC_CDB               0x03
#define    SC_TARGET_LUN        0x0F
#define    SC_PHASE             0x10
#define    SC_SYNC_XFER         0x11
#define    SC_COUNT_MSB         0x12
#define    SC_COUNT_ISB         0x13
#define    SC_COUNT_LSB         0x14
#define    SC_DEST              0x15
#define    SC_SOURCE_ID         0x16
#define    SC_STATUS            0x17
#define    SC_COMMAND           0x18
#define    SC_DATA              0x19
#define    SC_AUX               0x1F

#define    SBIC_FIFO_DEPTH	0x0c	/* size of SBIC FIFO */

/* a definition of the Command Set */ 

#define  C_RESET                            0x00
#define  C_ABORT                            0x01
#define  C_ASSERT_ATN                       0x02
#define  C_NEGATE_ACK                       0x03
#define  C_DISCONNECT                       0x04
#define  C_SELECT_WITH_ATN                  0x06
#define  C_SELECT_WITHOUT_ATN               0x07
#define  C_SELECT_AND_TRANSFER_WITH_ATN     0x08
#define  C_SELECT_AND_TRANSFER_WITHOUT_ATN  0x09
#define  C_SET_IDI                          0x0F
#define  C_TRANSFER_INFO                    0x20
#define  C_SINGLE_BYTE                      0x80
#define  C_INVALID                          0xFF
/* Definition of individual bits in the SBIC Registers */

/* Auxilliary Status Register */
#define   DBR      (1<<0)  /* Data Buffer Ready    */
#define   PE       (1<<1)  /* Parity Error         */
#define   CIP      (1<<4) /* Command In Progress  */
#define   BSY      (1<<5) /* SBIC Busy            */
#define   LCI      (1<<6) /* Last Command Ignored */
#define   INT      (1<<7) /* SBIC Interrupt       */

/* Own Id Register */
#define  ID        (1<<0)  /* 3 bits of SCSI Id          */
#define  EAF       (1<<3)  /* Enable Advanced Features   */
#define  EHP       (1<<4)  /* Enable Host Parity         */
#define  FS        (1<<6)  /* 2 bits of Frequency Select */

/* Control Register */
#define  HSP       (1<<0)  /* Halt on SCSI Parity Error   */
#define  HA        (1<<1)  /* Halt on ATN                 */
#define  IDI       (1<<2)  /* Intermediate Disconnect Irq */
#define  EDI       (1<<3)  /* Ending Disconnect Irq       */
#define  HHP       (1<<4)  /* Halt on Host Parity Error   */
#define  DMX       (1<<5)  /* 2 bits of DMA Select        */

/* Target LUN Register */
#define  TL        (1<<0)  /* 3 bits of Target LUN        */
#define  DOK       (1<<6)  /* Disconnect OK               */
#define  TLV       (1<<7)  /* Target must send ID message */

/* Destination Id Register */
#define  DI        (1<<0)  /* 3 bits of Destination Id */
#define  DPD       (1<<6)  /* Data Phases Direction    */
#define  SCC       (1<<7)  /* Select Command Chain     */

/* Source Id Register */
#define  SI        (1<<0)  /* 3 bits of Source Id      */
#define  DSP       (1<<5)  /* Disable Select Parity    */
#define  ES        (1<<6)  /* Enable Selection         */
#define  ER        (1<<7)  /* Enable Reselection       */

/* Timeout Register */
#define  TIMEOUT_FREQUENCY  100     /* no. of timeout units in 1 second */
#define  TIMEOUT_PERIOD     50      /* Selection Timeout */

/* SBIC Interrupt Status Groups */
#define  IG_MASK       0xF0
#define  IG_RESET      0x00  /* The SBIC is Reset       */
#define  IG_COMPLETE   0x10  /* Command Complete        */
#define  IG_PAUSED     0x20  /* Command Paused          */
#define  IG_TERMINATED 0x40  /* Command Terminated      */
#define  IG_SERVICE    0x80  /* SBIC Requires Attention */     

/* Unexpected Phase Indicators */
#define  P_MASK       0x07
#define  P_DATA_OUT   0x00
#define  P_DATA_IN    0x01
#define  P_COMMAND    0x02
#define  P_STATUS     0x03
#define  P_MSG_OUT    0x06
#define  P_MSG_IN     0x07


/* SBIC Interrupt Status Values */

/* Reset */
#define  I_RESET                              0x00
#define  I_ADVANCED_RESET                     0x01

/* Successful Completion */
#define  I_SELECT_OK                          0x11
#define  I_SELECT_AND_TRANSFER_OK             0x16
#define  IC_DATA_OUT                          0x18
#define  IC_DATA_IN                           0x19
#define  IC_COMMAND                           0x1A
#define  IC_STATUS                            0x1B
#define  IC_MSG_OUT                           0x1E
#define  IC_MSG_IN                            0x1F

/* Paused or Aborted */
#define  I_PAUSED_WITH_ACK                    0x20
#define  I_SAVE_DATA_POINTERS                 0x21
#define  I_SELECT_ABORTED                     0x22
#define  I_UNEXPECTED_RESELECT                0x27
#define  IA_DATA_OUT                          0x28
#define  IA_DATA_IN                           0x29
#define  IA_COMMAND                           0x2A
#define  IA_STATUS                            0x2B
#define  IA_MSG_OUT                           0x2E
#define  IA_MSG_IN                            0x2F

/* Terminated */
#define  I_INVALID_COMMAND                    0x40
#define  I_UNEXPECTED_DISCONNECT              0x41
#define  I_TIMEOUT                            0x42
#define  I_PARITY_ERROR_WITHOUT_ATN           0x43
#define  I_PARITY_ERROR_WITH_ATN              0x44
#define  I_PARITY_ERROR_IN_STATUS             0x47
#define  IT_DATA_OUT                          0x48
#define  IT_DATA_IN                           0x49
#define  IT_COMMAND                           0x4A
#define  IT_STATUS                            0x4B
#define  IT_MSG_OUT                           0x4E
#define  IT_MSG_IN                            0x4F

/* Service Required */
#define  I_RESELECT                           0x81
#define  I_DISCONNECT                         0x85
#define  IS_DATA_OUT                          0x88
#define  IS_DATA_IN                           0x89
#define  IS_COMMAND                           0x8A
#define  IS_STATUS                            0x8B
#define  IS_MSG_OUT                           0x8E
#define  IS_MSG_IN                            0x8F

/* Messages defined in the SCSI Spec */
#define  M_COMMAND_COMPLETE                   0x00
#define  M_EXTENDED_MESSAGE		      0x01
#define  M_SAVE_DATA_POINTERS                 0x02
#define  M_RESTORE_POINTERS                   0x03
#define  M_DISCONNECT                         0x04
#define  M_INITIATOR_DETECTED_ERROR           0x05
#define  M_ABORT                              0x06
#define  M_MESSAGE_REJECT                     0x07
#define  M_NOP                                0x08
#define  M_MESSAGE_PARITY_ERROR               0x09
#define  M_DEVICE_RESET                       0x0C
#define  M_IDENTIFY                           0x80

/* Parameters for Extended Messages */
#define EXTENDED_MESSAGE_LENGTH		      0x102
#define EM_SYNCHRONOUS_DATA_XFER_REQUEST      0x01

/* Additional bit in IDENTIFY message */
#define  M_RESELECTABLE                       0x40

/* Command Phases for Resuming Select and Transfer */
#define P_DISCONNECTED                        0x00
#define P_SELECTED                            0x10
#define P_ID_MSG_SENT                         0x20
#define P_CMD_PHASE                           0x30
#define P_AFTER_SAVE_DATA_POINTERS            0x41
#define P_AFTER_DISCONNECT_MSG                0x42
#define P_DISCONNECTED_OK                     0x43
#define P_AFTER_RESELECTION                   0x44
#define P_CONTINUE_TRANSFER                   0x45
#define P_EXPECTING_STATUS                    0x46
#define P_STATUS_PHASE                        0x50
#define P_CMD_COMPLETED                       0x60
#define P_AFTER_COMMAND_COMPLETE_MSG          0x60

/* Hardware state machine - states */
#define H_INITIALISING    0
#define H_INACTIVE        1
#define H_ACTIVE          2
#define H_ERROR           3
#define H_DISCONNECTING   4

/* Flag bits defined for SCSI_Command */
#define F_READ                  (1<<0)
#define F_WRITE                 (1<<1)
#define F_SENSE_VALID           (1<<2)
#define F_NO_SENSE              (1<<3)
#define F_COMMAND_COMPLETE      (1<<4)
#define F_ERROR                 (1<<5)
#define F_STATUS_VALID          (1<<6)
#define F_COMMAND_STARTED       (1<<7)
#define F_INTERNAL_COMMAND      (1<<8)
#define F_DUMMY_CMD             (1<<9)
#define F_PARITY_ERROR          (1<<10)
#define F_ALLOW_DISCONNECT	(1<<11)
#define F_PRESERVED_FLAGS	(F_READ | F_WRITE | F_NO_SENSE | \
				 F_ALLOW_DISCONNECT)

/* Flag bits defined for SCSI_Target */
#define T_COMMAND_READY         (1<<0)

/* different DEBUG bit masks */
#define DEBUG_IRQS		(1<<0)
#define DEBUG_SOFT_IRQS		(1<<1)
#define DEBUG_DMAC		(1<<2)
#define DEBUG_COPY		(1<<3)
#define DEBUG_DRIVER		(1<<4)
#define DEBUG_QUEUE		(1<<5)
#define DEBUG_DEVICE		(1<<6)
#define DEBUG_MINIMUM		(1<<8)

/* SBIC Access Macros */
#define put(chip, value)        (chip)->rd.reg = (value)
#define get(chip)               (chip)->rd.reg
#define get_aux(chip)           (chip)->rc.aux_status.reg

#define set_reg(chip, name)     (chip)->rc.address.reg = SC_/**/name
#define do_l1(chip, cmd)         while ((get_aux(chip) & CIP) != 0); set_reg(chip, COMMAND); put(chip, cmd)
#define do_l2(chip, cmd)         while ((get_aux(chip) & (BSY+CIP)) != 0); set_reg(chip, COMMAND); put(chip, cmd)
#define get_reg(chip, reg)      (set_reg(chip, reg), get(chip))
#define put_reg(chip, reg, val) (set_reg(chip, reg), put(chip, val))

/* The Interrupt Handler */
extern void scsi_irq( /* int podule */ );
extern int  scsi_int( /* int podule */ );

/* Soft Interrupt Raising Mechanism */
extern void raise_soft_irq( /* argument */ );
extern int  soft_count; /* number of soft interrupts raised */

/* debugging variable */
extern int ps_scsi_debug;
#define DoDebug(x)		(ps_scsi_debug & (x))

#endif/*__dev_ps_irq_h*/

/* EOF ps_irq.h */
