/* rcsid: $Revision: 1.2 $ */
/*
 * Device driver definitions for 4 port Nymos serial card
 *
 * Based on iecs.h,
 * Copywright, 1989 Imaginary Devices Ltd.
 *
 * Copyright (c) The Instruction Set Ltd, 1989
 */

/*
 * Header file defining the main programming interface of the Nymos 4 port
 * card.
 * The controller is based on the SCC 2691 UART chip
 */

/* Number of 2691 UARTs on each card */
#define LINES_PER_CARD  4

/*
 * UART registers
 */
typedef struct dev_2691 {
	volatile u_char	uart_mrn;	/* Mode Register 1/2 */
	u_char	uart_fillmrn[3];
	volatile u_char	uart_csr;	/* Clock Select Register / Status register */
	u_char	uart_fillcsr[3];
	volatile u_char	uart_cr;	/* Command Register */
	u_char	uart_fillcr[3];
	volatile u_char	uart_thr;	/* Receive/Transmit Holding Register */
	u_char	uart_fillthr[3];
	volatile u_char	uart_acr;	/* Auxillary Control Register */
	u_char	uart_fillacr[3];
	volatile u_char	uart_imr;	/* Interrupt Status/Mask Register */
	u_char	uart_fillimr[3];
	volatile u_char	uart_ctur;	/* Counter/timer Upper byte */
	u_char	uart_fillctur[3];
	volatile u_char	uart_ctul;	/* Counter/timer Lower byte */
	u_char	uart_fillctul[3];
} *dev_2961;

/*
 * some register are different depending on read/write
 */
#define uart_sr		uart_csr
#define uart_rhr	uart_thr
#define uart_isr	uart_imr

/*
 * Bit definitions for each register
 */
#define	MR1_RXRTS	0x80
#define	MR1_RXINT	0x40
#define	MR1_ERRMODE	0x20
#define	MR1_PARMODE	0x18
#define	MR1_PARTYPE	0x4
#define	MR1_BPC		0x3

/* rx int select */
#define MR1_RXRDY	0
#define	MR1_FFULL	MR1_RXINT
/* error mode */
#define	MR1_CHAR	0
#define MR1_BLOCK	MR1_ERRMODE
/* parity mode */
#define	MR1_PAREN	0
#define	MR1_PARFRC	0x8
#define MR1_NOPAR	0x10
#define	MR1_PARSPCL	0x18
/* parity type */
#define	MR1_EVEN	0
#define MR1_ODD		MR1_PARTYPE
/* bits per char */
#define MR1_5BIT	0
#define	MR1_6BIT	0x1
#define	MR1_7BIT	0x2
#define	MR1_8BIT	0x3

/*
 * Mode register 2
 */
#define	MR2_CHANMODE	0xC0
#define	MR2_TXRTS	0x20
#define	MR2_CTSTX	0x10
#define	MR2_STOPBITS	0xf

/* channel mode */
#define MR2_NORMAL	0
#define MR2_ECHO	0x40
#define	MR2_LLOOP	0x80
#define	MR2_RLOOP	0xC0

/* stop bits usually used */
#define	MR2_1STOP	7
#define	MR2_2STOP	0xf

/* Clock Select Register */
#define	CSR_RXCLOCK	0xF0
#define CSR_TXCLOCK	0x0F

/* Control Register */
#define	CR_MISC		0xF0
#define	CR_DISTX	0x8
#define CR_ENATX	0x4
#define CR_DISRX	0x2
#define CR_ENARX	0x1

/* misc cmd bits */
#define	CR_MISC_SHIFT	4
#define	CR_RESET	(1 << CR_MISC_SHIFT)
#define CR_RXRST	(2 << CR_MISC_SHIFT)
#define	CR_TXRST	(3 << CR_MISC_SHIFT)
#define	CR_ERRRST	(4 << CR_MISC_SHIFT)
#define	CR_BRKRST	(5 << CR_MISC_SHIFT)
#define	CR_STRTBRK	(6 << CR_MISC_SHIFT)
#define CR_STOPBRK	(7 << CR_MISC_SHIFT)
#define	CR_STRTCTR	(8 << CR_MISC_SHIFT)
#define	CR_STOPCTR	(9 << CR_MISC_SHIFT)
#define	CR_RTSNON	(10 << CR_MISC_SHIFT)
#define	CR_RTSNOFF	(11 << CR_MISC_SHIFT)
#define	CR_MPIRST	(12 << CR_MISC_SHIFT)

/* Status Register */
#define	SR_RXBRK	0x80
#define	SR_FRMER	0x40
#define	SR_PARER	0x20
#define	SR_OVERR	0x10
#define	SR_TXEMT	0x8
#define	SR_TXRDY	0x4
#define	SR_FFULL	0x2
#define	SR_RXRDY	0x1

/* Auxillary Control Register */
#define	ACR_BRGSET	0x80
#define	ACR_CTRMODE	0x70
#define	ACR_PWRDWN	0x8
#define	ACR_MPO		0x7
/* Baud rate generator set values */
#define ACR_BRG0	0
#define	ACR_BRG1	ACR_BRGSET
/* multi-purpose output pin uses */
#define	ACR_RTSN	0
#define	ACR_CTO		0x1
#define	ACR_TXC1	0x2
#define	ACR_TXC16	0x3
#define	ACR_RXC1	0x4
#define	ACR_RXC16	0x5
#define	ACR_TXRDY	0x6
#define	ACR_RXRDY	0x7
#define	ACR_FFULL	0x7

/* Interrupt Status Register */
#define	ISR_MPICHNG	0x80
#define	ISR_MPISTATE	0x40
#define	ISR_CTRRDY	0x10
#define	ISR_DELBRK	0x8
#define	ISR_RXRDY	0x4
#define	ISR_TXEMT	0x2
#define	ISR_TXRDY	0x1

/* Interrupt Mask Register */
#define	IMR_MPICHNG	ISR_MPICHNG
#define	IMR_MPILVL	ISR_MPISTATE
#define	IMR_CTRRDY	ISR_CTRRDY
#define	IMR_DELBRK	ISR_DELBRK
#define IMR_RXRDY	ISR_RXRDY
#define	IMR_TXEMT	ISR_TXEMT
#define	IMR_TXRDY	ISR_TXRDY

/* Normally required interrupt conditions */
#define RX_INTERRUPT	ISR_DELBRK | ISR_RXRDY
#define ANY_INTERRUPT	RX_INTERRUPT | ISR_TXEMT

/* Baud rate values NB dependant on ACR_BRGSET */
#define	NYM_B50		0
#define	NYM_B75		0
#define	NYM_B110	1
#define	NYM_B1345	2
#define	NYM_B150	3
#define	NYM_B200	3
#define	NYM_B300	4
#define	NYM_B600	5
#define	NYM_B1050	7
#define	NYM_B1200	6
#define	NYM_B1800	10
#define	NYM_B2000	7
#define	NYM_B2400	8
#define	NYM_B4800	9
#define	NYM_B7200	10
#define	NYM_B9600	11
#define	NYM_B19200	12
#define	NYM_B38400	12

/*
 * Address of the Uart register set.  This is relative to the
 * card slot start address in XCB I/O space - our card is operated
 * with medium-speed I/O cycles.
 */

#define UART_ADDR(slot, line) \
    ((dev_2961)(XCB_ADDRESS(SLOW,slot) + (0x2000+0x400*(line))))

/* EOF nym.h */
