/*
 * $Header: /smsa/bsd:include/dev/acia.h:bsd  1.5  $
 * $Source: /smsa/bsd:include/dev/acia.h: $
 *
 * Copyright (c) 1988 Acorn Computers Ltd., Cambridge, England
 */

#ifndef __dev_acia_h
#define __dev_acia_h

/* acia.h
 *
 * Definition of the ACIA on A500 (a 65C51)
 *
 */


/*
 * ACIA register memory-map
 */

typedef	struct
{
    volatile unsigned char
	data,    pad_1[3],			/* RX data (R) TX data (W) */
	status,  pad_2[3],			/* status reg (R) / reset (W) */
	command, pad_3[3],			/* command reg (R/W) */
	control, pad_4[3];			/* control reg (R/W */
} *ACIARef;


/*
 * Bits in ACIA status register
 *
 * Interrupt-generating bits; IRQ bit is OR of the others and reflects
 * the state of the SLCI input to IOC.
 */

#define ACIA_STAT_IRQ   (1 << 7)     /* 1 -> interrupt outstanding */
#define ACIA_STAT_DSR   (1 << 6)     /* Data Set Ready (Active LOW) */
#define ACIA_STAT_DCD   (1 << 5)     /* Data Carrier Detect (Active LOW) */
#define ACIA_STAT_TDRE  (1 << 4)     /* 1:transmitter completed */
#define ACIA_STAT_RDRF  (1 << 3)     /* 1:receiver ready with data */

/*
 * Non interrupt-generating bits - these indicate errors in
 * received data and are cleared on rx data read.
 */

#define ACIA_STAT_OVRN  (1 << 2)     /* overrun error bit */
#define ACIA_STAT_FE    (1 << 1)     /* framing error bit */
#define ACIA_STAT_PE    (1 << 0)     /* parity error bit */

/*
 * Bits in ACIA command register - read/write
 */

#define	ACIA_CMD_PMC	(3 << 6)	/* Parity Mode Control bits */
					/* values for these are: */
#define	ACIA_PMC_ODD	(0 << 6)	/*   00 - odd parity */
#define	ACIA_PMC_EVEN	(1 << 6)	/*   01 - even parity */
#define	ACIA_PMC_MARK	(2 << 6)	/*   10 - mark on tx, no check on rx */
#define	ACIA_PMC_SPACE	(3 << 6)	/*   11 - space on tx, no check on rx */

#define ACIA_CMD_PME	(1 << 5)	/* Parity Mode Enable 0:off 1:on */
#define ACIA_CMD_REM	(1 << 4)	/* Receiver Echo Mode 0:off 1:on */

#define ACIA_CMD_TIC	(3 << 2)	/* Transmitter Interrupt Control bits */
					/* values for these are: */
#define ACIA_TIC_NTX_NRTS	(0 << 2)/*   00 - tx off, rts low */
#define ACIA_TIC_TX_RTS		(1 << 2)/*   01 - tx on, rts high */
#define ACIA_TIC_NTX_RTS	(2 << 2)/*   10 - tx off, rts high */
#define	ACIA_TIC_NTX_RTS_BRK	(3 << 2)/*   11 - tx off, rts high, break */

#define	ACIA_CMD_RID	(1 << 1)	/* Receiver Interrupt Disable */
#define	ACIA_CMD_DTR	(1 << 0)	/* Data Terminal Ready control */

/* bits in ACIA control register - read/write */

#define	ACIA_CON_SBN	(1 << 7)	/* Number of Stop Bits bit */
#define	ACIA_CON_WL	(3 << 5)	/* Word Length bits */
#define	ACIA_WL_8	(0 << 5)	/*   00 - 8 bits */
#define	ACIA_WL_7	(1 << 5)	/*   01 - 7 bits */
#define	ACIA_WL_6	(2 << 5)	/*   10 - 6 bits */
#define	ACIA_WL_5	(3 << 5)	/*   11 - 5 bits */

#define ACIA_CON_RCS	(1 << 4)	/* Receiver Clock Source 0:ext, 1:int */

/*
 * Tx baud rates - when RCS is high, controls Rx clock also.
 */

#define ACIA_CON_SPEED	0xF			/* 4 bit field */
#define ACIA_SPEED_EXT	0x0			/* 16x external clock */
#define ACIA_SPEED_50	0x1
#define ACIA_SPEED_75	0x2
#define ACIA_SPEED_110	0x3
#define ACIA_SPEED_134	0x4
#define ACIA_SPEED_150	0x5
#define ACIA_SPEED_300	0x6
#define ACIA_SPEED_600	0x7
#define ACIA_SPEED_1200	0x8
#define ACIA_SPEED_1800	0x9
#define ACIA_SPEED_2400	0xA
#define ACIA_SPEED_3600	0xB
#define ACIA_SPEED_4800	0xC
#define ACIA_SPEED_7200	0xD
#define ACIA_SPEED_9600	0xE
#define ACIA_SPEED_19200 0xF

/* Where the ACIA lives in A500 I/O space */

#define	ACIA	((ACIARef)0x033B0000)

/*
 *	Reset operation - caused by write to status reg location
 */

#define	reset_acia(a)	a->status = 0

#endif/*__dev_acia_h*/

/* EOF acia.h */
